The approaches described in this section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
In certain applications, memory circuitry may need to be refreshed periodically with the same values. One example application where this may occur is for Reed-Solomon forward error correction (FEC) operating in a 100 GB/s or 400 GB/s Ethernet link (referred to as 100GE and 400GE respectively).
In an example implementation, Reed-Solomon ECC circuitry may require calculation of inverse values of a finite field for different algorithms such as the Forney algorithm or the Berlekamp-Massey algorithm. An implementation of Reed-Solomon ECC circuitry on programmable circuitry, such as a field programmable gate array (FPGA), may include using many parallel memory blocks configured as read-only memories (ROMs) to perform lookups for the appropriate inverse values that are calculated and stored in the parallel memory blocks. Some implementations of the Reed-Solomon ECC block would include 33 and 128 parallel memories for 100GE and 400GE, respectively.
Large Reed-Solomon ECC circuitry would require large parallel memories. However, the problem with larger memories used as ROMs is that error conditions such as single event upsets (SEUs) are left uncorrected because error correction would require a large amount of circuitry. In fact, for large Reed-Solomon circuitry with large parallel memories, the error correction circuitry may cost as much as the rest of the Reed-Solomon circuitry.